1. Technical Field
The invention relates to non-volatile RAM structures and more specifically to non-volatile structures using nanotube electromechanical (NT) switches to provide unit cells that may be employed in integrated circuits.
2. Discussion of Related Art
Important characteristics for a memory cell in electronic devices include low cost, non-volatility, high density, low power, and high speed. Conventional memories exhibit some, but not all, of these important characteristics. Examples of conventional memories include Read Only Memory (ROM), Programmable Read only Memory (PROM), Electrically Programmable Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). Some of the difficulties found within conventional memories are the following.
ROM is relatively low cost but cannot be rewritten. PROM can be electrically programmed, but PROM can be only be programmed once. EPROM maintains fast read cycles relative to ROM and PROM. However, EPROM exhibits a reliability limited to a few iterative read/write cycles and long erase times. EEPROM has low power consumption and is inexpensive, but has long write cycles (ms) and slow speed relative to DRAM or SRAM. Flash memory is faster than EEPROM but still incurs the same detriments as EEPROM. Flash memory also has a finite number of read/write cycles giving rise to low long-term reliability.
ROM, PROM, EPROM and EEPROM are all non-volatile memories. Non-volatile memory retains information stored in the memory cells, if an interruption in power occurs.
DRAM stores charge on transistor gates that act as capacitors, but DRAM must be electrically refreshed every few milliseconds thereby complicating system design by requiring separate circuitry to refresh the memory contents before the capacitors discharge.
SRAM is faster than DRAM and does not need to be refreshed. Yet, SRAM has lower density and higher cost than DRAM. Both SRAM and DRAM are volatile memories. Volatile memory loses information stored in the memory cells, if an interruption in power occurs.
Existing memory technologies can be classified into two categories, volatile and non-volatile. Non-volatile memories are not randomly accessible and do not support multiple writes with any high degree of reliability. In addition, non-volatile memories have low density and high cost. Volatile memories have either complicated system design or have low density.
Emerging technologies have attempted to address these shortcomings. Magnetic RAM (MRAM) or ferromagnetic RAM (FRAM) utilizes the orientation of magnetization or a ferromagnetic region to generate a non-volatile memory cell. Both of these types of memory cells have high magneto-resistance and low density.
MRAM utilizes a magneto-resistive memory element involving the anisotropic magneto-resistance or giant magneto-resistance of ferromagnetic materials to achieve a non-volatile memory cell. A different memory cell based upon magnetic tunnel junctions has also been examined but has not led to large-scale commercialized MRAM devices.
FRAM uses a circuit architecture similar to DRAM by storing charge on a capacitor. A thin film ferroelectric capacitor retains an electrical polarization after an externally applied electric field is removed. The retention in polarization yields a nonvolatile memory cell. FRAM suffers from a large memory cell size, and it is difficult to manufacture as a large-scale integrated component.
Phase change memory is another non-volatile memory. Phase change memory stores within the states of the lattice (i.e., atomic structure) of thin-film alloys containing elements, such as, selenium or tellurium. These alloys remain stable in both crystalline and amorphous states allowing the formation of a bi-stable switch. Unfortunately, phase change memory suffers from slow operations and questionable reliability. Phase change memory is also difficult to manufacture and, consequently, has not been commercialized.
Another memory technology being explored is molecular wire crossbar memory (MWCM). MWCM researchers envision using molecules as bi-stable switches. A thin layer (a few atoms thick) of molecular compounds is sandwiched between two wires (metal or semiconductor). Chemical assembly techniques are used to precisely synthesize the atomic layer. Chemical assembly techniques exploits non-equilibrium conditions of chemical reactions between external reagents and surface functional groups. Electrochemical oxidation/reduction (ox/redox) is used in conjunction with chemical assembly techniques to generate an on or off state. Inherent within redox processes, this form of memory can be unstable (volatile) and requires highly specialized wire junctions.
Recently, memory devices have been proposed which use nanoscopic wires, such as single-walled carbon nanotubes, to form crossbar junctions to serve as memory cells. See PCT patent application No. WO 01/03208 entitled “Nanoscopic Wire-Based Devices, Arrays, and Methods of Their Manufacture” and “Carbon Nanotube-Based Nonvolatile Random Access Memory for Molecular Computing,” published in Science, vol. 289, pp. 94-97, 7 Jul., 2000.
The above identified references describe individual single-walled nanotube (SWNT) wires suspended over other wires to define memory cells. Responsive to electrical signals, the wires physically attract or repel one another. Each physical state (i.e., attracted or repelled wires) corresponds to an electrical state. Repelled wires are an open circuit junction. Attracted wires are a closed state forming a rectified junction. When electrical power is removed from the junction, the wires retain their physical (and thus electrical) state thereby forming a non-volatile memory cell.
Nanotube wire crossbar memories (NTWCMs) rely on directed growth or chemical self-assembly techniques to grow the individual nanotubes needed for the memory cells. These techniques are now believed to be difficult to employ at commercial scales using modern technology. Moreover, they may contain inherent limitations such as the length of the nanotubes that may be grown reliably using these techniques, and it may difficult to control the statistical variance of geometries of nanotube wires so grown.
The ideal memory for at least some purposes is one which would offer low cost per bit, high density, fast random access, read/write cycle times of equal duration, low power consumption, operation over a wide temperature range, a single low-voltage power supply, with a high degree of radiation tolerance. The non-volatile described herein cell offers high speed read, but also high speed write (nanosecond) vs. the slow (microsecond & millisecond) write time of EEPROM and FLASH EEPROM type of memories. The memory is much denser than conventional SRAM because it has a two device, NT and 3 array line structure, and offers competitive performance. The density is less than that of DRAM cells, however, the product offers NDRO operation and non-volatility.
U.S. Patent Publication No. 2003-0021966 discloses, among other things, electromechanical circuits, such as memory cells, in which circuits include a structure having electrically conductive traces and supports extending from a surface of a substrate. Nanotube ribbons are suspended by the supports that cross the electrically conductive traces. Each ribbon comprises one or more nanotubes. The ribbons are formed from selectively removing material from a layer or matted fabric of nanotubes.
For example, as disclosed in U.S. Patent Application Publication No. 2003-0021966, a nanofabric may be patterned into ribbons, and the ribbons can be used as a component to create non-volatile electromechanical memory cells. The ribbon is electromechanically-deflectable in response to electrical stimulus of control traces and/or the ribbon. The deflected, physical state of the ribbon may be made to represent a corresponding information state. The deflected, physical state has non-volatile properties, meaning the ribbon retains its physical (and therefore informational) state even if power to the memory cell is removed. As explained in U.S. Patent Application Publication No. 2003-0124325, three-trace architectures may be used for electromechanical memory cells, in which the two of the traces are electrodes to control the deflection of the ribbon.